:: commit 69f97ecfd5b4a3eb0ff5ef26e33657f7b477c0de

diff --git a/PROTOCOL.md b/PROTOCOL.md
index c731b7ad..0c52cc06 100644
--- a/PROTOCOL.md
+++ b/PROTOCOL.md
@@ -149,7 +149,7 @@ The `MAIR_EL1` register will at least contain entries for the above-mentioned
 caching modes, in an unspecified order.
 
 In order to access MMIO regions, the kernel must ensure the correct caching mode
-is used on it's own.
+is used on its own.
 
 ### riscv64
 
@@ -213,7 +213,7 @@ unless the an Entry Point feature is requested (see below), in which case,
 the value of `PC` is going to be taken from there.
 
 The contents of the `VBAR_EL1` register are undefined, and the kernel must load
-it's own.
+its own.
 
 The `MAIR_EL1` register contents are described above, in the caching section.