:: commit 5b9a43d6841b940f4e16e9edb9dd7c7aa5b9fed0

diff --git a/limine-pxe.bin b/limine-pxe.bin
index bbb557a5..ff180440 100644
Binary files a/limine-pxe.bin and b/limine-pxe.bin differ
diff --git a/limine.bin b/limine.bin
index c9bd37cf..b04497a2 100644
Binary files a/limine.bin and b/limine.bin differ
diff --git a/stage2.map b/stage2.map
index 5c84fd16..6b046cfd 100644
Binary files a/stage2.map and b/stage2.map differ
diff --git a/stage2/mm/vmm.c b/stage2/mm/vmm.c
index a0728bac..46c59eb6 100644
--- a/stage2/mm/vmm.c
+++ b/stage2/mm/vmm.c
@@ -44,13 +44,17 @@ void map_page(pagemap_t pagemap, uint64_t virt_addr, uint64_t phys_addr, uint64_
     switch (pagemap.levels) {
         case 5:
             pml5 = pagemap.top_level;
-            pml4 = get_next_level(pml5, pml5_entry);
-            break;
+            goto level5;
         case 4:
             pml4 = pagemap.top_level;
-            break;
+            goto level4;
+        default:
+            panic("");
     }
 
+level5:
+    pml4 = get_next_level(pml5, pml5_entry);
+level4:
     pml3 = get_next_level(pml4, pml4_entry);
     pml2 = get_next_level(pml3, pml3_entry);
 
diff --git a/stage2/protos/stivale.c b/stage2/protos/stivale.c
index 694b9911..a5f96dfc 100644
--- a/stage2/protos/stivale.c
+++ b/stage2/protos/stivale.c
@@ -51,13 +51,11 @@ void stivale_load(char *cmdline) {
         case 64: {
             // Check if 64 bit CPU
             uint32_t eax, ebx, ecx, edx;
-            cpuid(0x80000001, 0, &eax, &ebx, &ecx, &edx);
-            if (!(edx & (1 << 29))) {
+            if (!cpuid(0x80000001, 0, &eax, &ebx, &ecx, &edx) || !(edx & (1 << 29))) {
                 panic("stivale: This CPU does not support 64-bit mode.");
             }
             // Check if 5-level paging is available
-            cpuid(0x00000007, 0, &eax, &ebx, &ecx, &edx);
-            if (ecx & (1 << 16)) {
+            if (cpuid(0x00000007, 0, &eax, &ebx, &ecx, &edx) && (ecx & (1 << 16))) {
                 print("stivale: CPU has 5-level paging support\n");
                 level5pg = true;
             }
diff --git a/stage2/protos/stivale2.c b/stage2/protos/stivale2.c
index 2b2e7c71..9addfabe 100644
--- a/stage2/protos/stivale2.c
+++ b/stage2/protos/stivale2.c
@@ -74,14 +74,12 @@ void stivale2_load(char *cmdline) {
         case 64: {
             // Check if 64 bit CPU
             uint32_t eax, ebx, ecx, edx;
-            cpuid(0x80000001, 0, &eax, &ebx, &ecx, &edx);
-            if (!(edx & (1 << 29))) {
-                panic("stivale2: This CPU does not support 64-bit mode.");
+            if (!cpuid(0x80000001, 0, &eax, &ebx, &ecx, &edx) || !(edx & (1 << 29))) {
+                panic("stivale: This CPU does not support 64-bit mode.");
             }
             // Check if 5-level paging is available
-            cpuid(0x00000007, 0, &eax, &ebx, &ecx, &edx);
-            if (ecx & (1 << 16)) {
-                print("stivale2: CPU has 5-level paging support\n");
+            if (cpuid(0x00000007, 0, &eax, &ebx, &ecx, &edx) && (ecx & (1 << 16))) {
+                print("stivale: CPU has 5-level paging support\n");
                 level5pg = true;
             }
 
diff --git a/stage2/sys/smp.c b/stage2/sys/smp.c
index 90c48c98..53f847de 100644
--- a/stage2/sys/smp.c
+++ b/stage2/sys/smp.c
@@ -124,7 +124,7 @@ struct smp_information *init_smp(size_t    header_hack_size,
 
     x2apic = x2apic && x2apic_enable();
 
-    uint32_t bsp_x2apic_id;
+    uint32_t bsp_x2apic_id = 0;
     if (x2apic) {
         // The Intel manual recommends checking if leaf 0x1f exists first, and
         // using that in place of 0xb if that's the case