:: commit 704dd7ee250d5c9b1b7974fe2aa140abbd3a3d77
protos/limine: Make the PAT non-mandatory and check for support before using it
Additionally, move the PAT enabling code to the code that runs in a non-paged mode in order to avoid potential weird issues with cache flushing
diff --git a/PROTOCOL.md b/PROTOCOL.md
index 309e7052..96e12cb4 100644
--- a/PROTOCOL.md
+++ b/PROTOCOL.md
@@ -207,7 +207,7 @@ All HHDM and identity map memory regions are mapped using write-back (WB) cachin
tables level, except framebuffer regions which are mapped using write-combining
(WC) caching at the page tables level.
-The PAT's (Page Attribute Table) layout is specified to be as follows:
+If the CPU supports the PAT (Page Attribute Table), its layout is specified to be as follows:
```
PAT0 -> WB
PAT1 -> WT
diff --git a/common/protos/limine.c b/common/protos/limine.c
index 1f0361da..d668ba2a 100644
--- a/common/protos/limine.c
+++ b/common/protos/limine.c
@@ -1503,16 +1503,6 @@ FEAT_END
rm_int(0x15, &r, &r);
#endif
- // Set PAT as:
- // PAT0 -> WB (06)
- // PAT1 -> WT (04)
- // PAT2 -> UC- (07)
- // PAT3 -> UC (00)
- // PAT4 -> WP (05)
- // PAT5 -> WC (01)
- uint64_t pat = (uint64_t)0x010500070406;
- wrmsr(0x277, pat);
-
pic_mask_all();
io_apic_mask_all();
diff --git a/common/protos/limine_32.asm_x86 b/common/protos/limine_32.asm_x86
index 797ad787..3d98d19b 100644
--- a/common/protos/limine_32.asm_x86
+++ b/common/protos/limine_32.asm_x86
@@ -4,6 +4,24 @@ section .text
global limine_spinup_32
limine_spinup_32:
+ ; If available, set PAT as:
+ ; PAT0 -> WB (06)
+ ; PAT1 -> WT (04)
+ ; PAT2 -> UC- (07)
+ ; PAT3 -> UC (00)
+ ; PAT4 -> WP (05)
+ ; PAT5 -> WC (01)
+ mov eax, 1
+ xor ecx, ecx
+ cpuid
+ test edx, 1 << 16
+ jz .no_pat
+ mov eax, 0x00070406
+ mov edx, 0x00000105
+ mov ecx, 0x277
+ wrmsr
+ .no_pat:
+
; Enable EFER.NXE
cmp dword [esp+32], 0 ; nx_available
je .no_nx
