riscv: Do an early RISC-V init to allow checking ISA features early
diff --git a/common/entry.s3.c b/common/entry.s3.c
index 9eb2497d..f6422d4c 100644
--- a/common/entry.s3.c
+++ b/common/entry.s3.c
@@ -186,6 +186,8 @@ noreturn void stage3_common(void) {
if (rv_proto == NULL || rv_proto->GetBootHartId(rv_proto, &bsp_hartid) != EFI_SUCCESS) {
panic(false, "failed to get BSP's hartid");
}
+
+ init_riscv(NULL);
#else
#error riscv: only UEFI is supported
#endif
diff --git a/common/lib/misc.c b/common/lib/misc.c
index 73a8a2aa..851a018c 100644
--- a/common/lib/misc.c
+++ b/common/lib/misc.c
@@ -146,7 +146,7 @@ void *get_device_tree_blob(const char *config, size_t extra_size) {
void *dtb = NULL;
{
- char *dtb_path = config_get_value(config, 0, "DTB_PATH");
+ char *dtb_path = config_get_value(config, 0, config ? "dtb_path" : "loader_dtb_path");
if (dtb_path) {
struct file_handle *dtb_file;
if ((dtb_file = uri_open(dtb_path)) == NULL)
diff --git a/common/sys/cpu_riscv.c b/common/sys/cpu_riscv.c
index dfe38593..3513dde8 100644
--- a/common/sys/cpu_riscv.c
+++ b/common/sys/cpu_riscv.c
@@ -58,8 +58,9 @@ struct rhct_mmu {
} __attribute__((packed));
size_t bsp_hartid;
-struct riscv_hart *hart_list;
+struct riscv_hart *hart_list = NULL;
static struct riscv_hart *bsp_hart;
+static const char *current_config = NULL;
static struct riscv_hart *riscv_get_hart(size_t hartid) {
for (struct riscv_hart *hart = hart_list; hart != NULL; hart = hart->next) {
@@ -225,6 +226,12 @@ static void init_riscv_fdt(const void *fdt) {
}
void init_riscv(const char *config) {
+ while (hart_list != NULL && current_config != config) {
+ void *cur_hart = hart_list;
+ hart_list = hart_list->next;
+ pmm_free(cur_hart, sizeof(struct riscv_hart));
+ }
+
void *fdt = get_device_tree_blob(config, 0);
if (fdt != NULL) {
init_riscv_fdt(fdt);
@@ -248,6 +255,8 @@ void init_riscv(const char *config) {
hart->flags |= RISCV_HART_COPROC;
}
}
+
+ current_config = config;
}
struct isa_extension {
