| 1 | #if defined (__x86_64__) && defined (UEFI) |
| 2 | |
| 3 | #include <stdint.h> |
| 4 | #include <stddef.h> |
| 5 | #include <stdbool.h> |
| 6 | #include <mm/efi_pt.h> |
| 7 | #include <mm/pmm.h> |
| 8 | #include <sys/cpu.h> |
| 9 | |
| 10 | #define PTE_P ((uint64_t)1 << 0) |
| 11 | #define PTE_RW ((uint64_t)1 << 1) |
| 12 | #define PTE_US ((uint64_t)1 << 2) |
| 13 | #define PTE_PWT ((uint64_t)1 << 3) |
| 14 | #define PTE_PCD ((uint64_t)1 << 4) |
| 15 | #define PTE_PS ((uint64_t)1 << 7) |
| 16 | #define PTE_PAT_4K ((uint64_t)1 << 7) |
| 17 | #define PTE_PAT_BIG ((uint64_t)1 << 12) |
| 18 | #define PTE_NX ((uint64_t)1 << 63) |
| 19 | #define PT_ADDR_MASK ((uint64_t)0x000FFFFFFFFFF000) |
| 20 | |
| 21 | #define IA32_PAT_MSR 0x277 |
| 22 | #define PAT_TYPE_WC 0x01 |
| 23 | |
| 24 | static bool la57_enabled(void) { |
| 25 | uint64_t cr4; |
| 26 | asm volatile ("mov %%cr4, %0" : "=r"(cr4)); |
| 27 | return !!(cr4 & ((uint64_t)1 << 12)); |
| 28 | } |
| 29 | |
| 30 | static bool gib_pages_supported(void) { |
| 31 | uint32_t eax, ebx, ecx, edx; |
| 32 | return cpuid(0x80000001, 0, &eax, &ebx, &ecx, &edx) && !!(edx & (1 << 26)); |
| 33 | } |
| 34 | |
| 35 | // Firmware PTEs we overwrote, replayed by efi_pt_restore() to undo the FB WC. |
| 36 | // On overflow we stop applying WC so the undo stays complete. |
| 37 | #define SAVED_PTES_MAX 1024 |
| 38 | |
| 39 | static uint64_t **saved_pte_ptr = NULL; |
| 40 | static uint64_t *saved_pte_val = NULL; |
| 41 | static size_t saved_pte_i = 0; |
| 42 | static uint64_t saved_pat = 0; |
| 43 | static bool pat_modified = false; |
| 44 | |
| 45 | static int wc_pat_index = -1; |
| 46 | static bool gib_supported = false; |
| 47 | |
| 48 | static bool save_pte(uint64_t *slot) { |
| 49 | if (saved_pte_i >= SAVED_PTES_MAX) { |
| 50 | return false; |
| 51 | } |
| 52 | saved_pte_ptr[saved_pte_i] = slot; |
| 53 | saved_pte_val[saved_pte_i] = *slot; |
| 54 | saved_pte_i++; |
| 55 | return true; |
| 56 | } |
| 57 | |
| 58 | // Caches off + TLB flushed for a safe PAT-MSR memory-type change. |
| 59 | static void cache_off(uint64_t *old_cr0) { |
| 60 | asm volatile ("mov %%cr0, %0" : "=r"(*old_cr0) :: "memory"); |
| 61 | asm volatile ("mov %0, %%cr0" |
| 62 | :: "r"((*old_cr0 | ((uint64_t)1 << 30)) & ~((uint64_t)1 << 29)) |
| 63 | : "memory"); |
| 64 | asm volatile ("wbinvd" ::: "memory"); |
| 65 | uint64_t cr3; |
| 66 | asm volatile ("mov %%cr3, %0" : "=r"(cr3) :: "memory"); |
| 67 | asm volatile ("mov %0, %%cr3" :: "r"(cr3) : "memory"); |
| 68 | } |
| 69 | |
| 70 | static void cache_on(uint64_t old_cr0) { |
| 71 | uint64_t cr3; |
| 72 | asm volatile ("mov %%cr3, %0" : "=r"(cr3) :: "memory"); |
| 73 | asm volatile ("mov %0, %%cr3" :: "r"(cr3) : "memory"); |
| 74 | asm volatile ("wbinvd" ::: "memory"); |
| 75 | asm volatile ("mov %0, %%cr0" :: "r"(old_cr0) : "memory"); |
| 76 | } |
| 77 | |
| 78 | // WP off to write read-only firmware PTEs; wp_on flushes the TLB to apply them. |
| 79 | static void wp_off(uint64_t *old_cr0) { |
| 80 | asm volatile ("mov %%cr0, %0" : "=r"(*old_cr0) :: "memory"); |
| 81 | asm volatile ("mov %0, %%cr0" :: "r"(*old_cr0 & ~((uint64_t)1 << 16)) : "memory"); |
| 82 | } |
| 83 | |
| 84 | static void wp_on(uint64_t old_cr0) { |
| 85 | // A plain CR3 reload leaves global TLB entries intact, so a firmware FB |
| 86 | // mapped with the global bit would keep its old memory type. Toggling |
| 87 | // CR4.PGE flushes the whole TLB including global entries (Intel SDM |
| 88 | // 4.10.4.1); fall back to a CR3 reload when PGE is off (no globals exist). |
| 89 | uint64_t cr4; |
| 90 | asm volatile ("mov %%cr4, %0" : "=r"(cr4) :: "memory"); |
| 91 | if (cr4 & ((uint64_t)1 << 7)) { |
| 92 | asm volatile ("mov %0, %%cr4" :: "r"(cr4 & ~((uint64_t)1 << 7)) : "memory"); |
| 93 | asm volatile ("mov %0, %%cr4" :: "r"(cr4) : "memory"); |
| 94 | } else { |
| 95 | uint64_t cr3; |
| 96 | asm volatile ("mov %%cr3, %0" : "=r"(cr3) :: "memory"); |
| 97 | asm volatile ("mov %0, %%cr3" :: "r"(cr3) : "memory"); |
| 98 | } |
| 99 | asm volatile ("mov %0, %%cr0" :: "r"(old_cr0) : "memory"); |
| 100 | } |
| 101 | |
| 102 | static int pte_pat_index(uint64_t e, bool leaf4k) { |
| 103 | uint64_t patbit = leaf4k ? PTE_PAT_4K : PTE_PAT_BIG; |
| 104 | return (!!(e & patbit) << 2) | (!!(e & PTE_PCD) << 1) | !!(e & PTE_PWT); |
| 105 | } |
| 106 | |
| 107 | // Non-leaf entries and CR3 have no PAT bit: typed by PCD/PWT only. |
| 108 | static int walk_pat_index(uint64_t e) { |
| 109 | return (!!(e & PTE_PCD) << 1) | !!(e & PTE_PWT); |
| 110 | } |
| 111 | |
| 112 | static void scan_walk(uint64_t *table, int lvl, uint8_t *used) { |
| 113 | for (size_t i = 0; i < 512; i++) { |
| 114 | if (*used == 0xff) { |
| 115 | return; |
| 116 | } |
| 117 | uint64_t e = table[i]; |
| 118 | if (!(e & PTE_P)) { |
| 119 | continue; |
| 120 | } |
| 121 | if ((lvl == 1) || (lvl <= 3 && (e & PTE_PS))) { |
| 122 | *used |= 1 << pte_pat_index(e, lvl == 1); |
| 123 | } else { |
| 124 | *used |= 1 << walk_pat_index(e); |
| 125 | scan_walk((uint64_t *)(e & PT_ADDR_MASK), lvl - 1, used); |
| 126 | } |
| 127 | } |
| 128 | } |
| 129 | |
| 130 | static uint8_t scan_used_pat_indices(void) { |
| 131 | uint64_t cr3; |
| 132 | asm volatile ("mov %%cr3, %0" : "=r"(cr3)); |
| 133 | uint8_t used = 1 << walk_pat_index(cr3); |
| 134 | scan_walk((uint64_t *)(cr3 & PT_ADDR_MASK), la57_enabled() ? 5 : 4, &used); |
| 135 | return used; |
| 136 | } |
| 137 | |
| 138 | // Reuse a WC slot if present, else repurpose one no live mapping selects. |
| 139 | static bool ensure_wc_pat_slot(void) { |
| 140 | if (wc_pat_index >= 0) { |
| 141 | return true; |
| 142 | } |
| 143 | |
| 144 | uint32_t eax, ebx, ecx, edx; |
| 145 | if (!cpuid(1, 0, &eax, &ebx, &ecx, &edx) || !(edx & (1 << 16))) { |
| 146 | return false; |
| 147 | } |
| 148 | |
| 149 | uint64_t pat = rdmsr(IA32_PAT_MSR); |
| 150 | |
| 151 | for (int i = 0; i < 8; i++) { |
| 152 | if (((pat >> (i * 8)) & 0xff) == PAT_TYPE_WC) { |
| 153 | wc_pat_index = i; |
| 154 | return true; |
| 155 | } |
| 156 | } |
| 157 | |
| 158 | uint8_t used = scan_used_pat_indices(); |
| 159 | |
| 160 | int slot = -1; |
| 161 | for (int i = 4; i < 8; i++) { |
| 162 | if (!(used & (1 << i))) { |
| 163 | slot = i; |
| 164 | break; |
| 165 | } |
| 166 | } |
| 167 | if (slot < 0) { |
| 168 | for (int i = 0; i < 4; i++) { |
| 169 | if (!(used & (1 << i))) { |
| 170 | slot = i; |
| 171 | break; |
| 172 | } |
| 173 | } |
| 174 | } |
| 175 | if (slot < 0) { |
| 176 | return false; |
| 177 | } |
| 178 | |
| 179 | saved_pat = pat; |
| 180 | pat_modified = true; |
| 181 | |
| 182 | pat = (pat & ~((uint64_t)0xff << (slot * 8))) |
| 183 | | ((uint64_t)PAT_TYPE_WC << (slot * 8)); |
| 184 | |
| 185 | uint64_t old_cr0; |
| 186 | cache_off(&old_cr0); |
| 187 | wrmsr(IA32_PAT_MSR, pat); |
| 188 | cache_on(old_cr0); |
| 189 | |
| 190 | wc_pat_index = slot; |
| 191 | return true; |
| 192 | } |
| 193 | |
| 194 | static uint64_t pte_set_pat(uint64_t e, int idx, bool leaf4k) { |
| 195 | uint64_t patbit = leaf4k ? PTE_PAT_4K : PTE_PAT_BIG; |
| 196 | e &= ~(PTE_PWT | PTE_PCD | patbit); |
| 197 | if (idx & 1) e |= PTE_PWT; |
| 198 | if (idx & 2) e |= PTE_PCD; |
| 199 | if (idx & 4) e |= patbit; |
| 200 | return e; |
| 201 | } |
| 202 | |
| 203 | // Children inherit the parent mapping so memory sharing the leaf keeps its type. |
| 204 | static uint64_t *split_leaf(uint64_t e, int lvl) { |
| 205 | uint64_t leaf_sz = (uint64_t)1 << ((lvl - 1) * 9 + 12); |
| 206 | uint64_t phys_base = e & PT_ADDR_MASK & ~(leaf_sz - 1); |
| 207 | int idx = pte_pat_index(e, false); |
| 208 | uint64_t flags = e & (PTE_P | PTE_RW | PTE_US | PTE_NX); |
| 209 | |
| 210 | int child_lvl = lvl - 1; |
| 211 | uint64_t child_sz = (uint64_t)1 << ((child_lvl - 1) * 9 + 12); |
| 212 | bool child_4k = child_lvl == 1; |
| 213 | |
| 214 | uint64_t *t = ext_mem_alloc(0x1000); |
| 215 | for (int i = 0; i < 512; i++) { |
| 216 | uint64_t c = (phys_base + (uint64_t)i * child_sz) | flags; |
| 217 | if (!child_4k) { |
| 218 | c |= PTE_PS; |
| 219 | } |
| 220 | t[i] = pte_set_pat(c, idx, child_4k); |
| 221 | } |
| 222 | return t; |
| 223 | } |
| 224 | |
| 225 | // pristine: inside firmware tables (saved); tables we allocate are not. |
| 226 | static void wc_walk(uint64_t *table, int lvl, uint64_t tbl_va, |
| 227 | uint64_t base, uint64_t end, bool pristine) { |
| 228 | uint64_t step = (uint64_t)1 << ((lvl - 1) * 9 + 12); |
| 229 | |
| 230 | for (size_t i = 0; i < 512; i++) { |
| 231 | uint64_t va = tbl_va + (uint64_t)i * step; |
| 232 | if (va >= end) { |
| 233 | break; |
| 234 | } |
| 235 | if (va + step <= base) { |
| 236 | continue; |
| 237 | } |
| 238 | |
| 239 | uint64_t *e = &table[i]; |
| 240 | bool present = !!(*e & PTE_P); |
| 241 | bool is_leaf = (lvl == 1) || (present && lvl <= 3 && (*e & PTE_PS)); |
| 242 | bool fully = va >= base && va + step <= end; |
| 243 | |
| 244 | if (fully && lvl <= 3 && (lvl < 3 || gib_supported)) { |
| 245 | uint64_t leaf; |
| 246 | if (present && is_leaf) { |
| 247 | leaf = (*e & PT_ADDR_MASK & ~(step - 1)) |
| 248 | | (*e & (PTE_P | PTE_RW | PTE_US | PTE_NX)); |
| 249 | } else { |
| 250 | leaf = va | PTE_P | PTE_RW; |
| 251 | } |
| 252 | if (lvl >= 2) { |
| 253 | leaf |= PTE_PS; |
| 254 | } |
| 255 | if (pristine && !save_pte(e)) { |
| 256 | continue; |
| 257 | } |
| 258 | *e = pte_set_pat(leaf, wc_pat_index, lvl == 1); |
| 259 | continue; |
| 260 | } |
| 261 | |
| 262 | if (present && !is_leaf) { |
| 263 | wc_walk((uint64_t *)(*e & PT_ADDR_MASK), lvl - 1, va, |
| 264 | base, end, pristine); |
| 265 | continue; |
| 266 | } |
| 267 | |
| 268 | if (pristine && !save_pte(e)) { |
| 269 | continue; |
| 270 | } |
| 271 | uint64_t *child; |
| 272 | if (present) { |
| 273 | child = split_leaf(*e, lvl); |
| 274 | } else { |
| 275 | child = ext_mem_alloc(0x1000); |
| 276 | } |
| 277 | *e = (uint64_t)child | PTE_P | PTE_RW | PTE_US; |
| 278 | wc_walk(child, lvl - 1, va, base, end, false); |
| 279 | } |
| 280 | } |
| 281 | |
| 282 | void efi_pt_set_fb_wc(uint64_t base, uint64_t size) { |
| 283 | if (size == 0) { |
| 284 | return; |
| 285 | } |
| 286 | |
| 287 | if (saved_pte_ptr == NULL) { |
| 288 | saved_pte_ptr = ext_mem_alloc(SAVED_PTES_MAX * sizeof(uint64_t *)); |
| 289 | saved_pte_val = ext_mem_alloc(SAVED_PTES_MAX * sizeof(uint64_t)); |
| 290 | } |
| 291 | |
| 292 | bool ints = disable_interrupts(); |
| 293 | |
| 294 | if (!ensure_wc_pat_slot()) { |
| 295 | goto out; |
| 296 | } |
| 297 | |
| 298 | uint64_t end = (base + size + 0xfff) & ~(uint64_t)0xfff; |
| 299 | base &= ~(uint64_t)0xfff; |
| 300 | |
| 301 | uint64_t cr3; |
| 302 | asm volatile ("mov %%cr3, %0" : "=r"(cr3)); |
| 303 | uint64_t *top = (uint64_t *)(cr3 & PT_ADDR_MASK); |
| 304 | int levels = la57_enabled() ? 5 : 4; |
| 305 | gib_supported = gib_pages_supported(); |
| 306 | |
| 307 | uint64_t old_cr0; |
| 308 | wp_off(&old_cr0); |
| 309 | wc_walk(top, levels, 0, base, end, true); |
| 310 | wp_on(old_cr0); |
| 311 | |
| 312 | out: |
| 313 | if (ints) { |
| 314 | enable_interrupts(); |
| 315 | } |
| 316 | } |
| 317 | |
| 318 | void efi_pt_restore(void) { |
| 319 | if (saved_pte_i == 0 && !pat_modified) { |
| 320 | goto out; |
| 321 | } |
| 322 | |
| 323 | bool ints = disable_interrupts(); |
| 324 | |
| 325 | if (saved_pte_i != 0) { |
| 326 | uint64_t old_cr0; |
| 327 | wp_off(&old_cr0); |
| 328 | for (size_t i = saved_pte_i; i-- > 0;) { |
| 329 | *saved_pte_ptr[i] = saved_pte_val[i]; |
| 330 | } |
| 331 | wp_on(old_cr0); |
| 332 | } |
| 333 | |
| 334 | if (pat_modified) { |
| 335 | uint64_t old_cr0; |
| 336 | cache_off(&old_cr0); |
| 337 | wrmsr(IA32_PAT_MSR, saved_pat); |
| 338 | cache_on(old_cr0); |
| 339 | } |
| 340 | |
| 341 | if (ints) { |
| 342 | enable_interrupts(); |
| 343 | } |
| 344 | |
| 345 | saved_pte_i = 0; |
| 346 | pat_modified = false; |
| 347 | wc_pat_index = -1; |
| 348 | |
| 349 | out: |
| 350 | if (saved_pte_ptr != NULL) { |
| 351 | pmm_free(saved_pte_ptr, SAVED_PTES_MAX * sizeof(uint64_t *)); |
| 352 | pmm_free(saved_pte_val, SAVED_PTES_MAX * sizeof(uint64_t)); |
| 353 | saved_pte_ptr = NULL; |
| 354 | saved_pte_val = NULL; |
| 355 | } |
| 356 | } |
| 357 | |
| 358 | #endif |
